1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a circuit for precharging bit lines.
2. Description of the Related Art.
In highly integrated semiconductor memory devices, integrated circuits must necessarily be capable of high speed operation. However, memory cell sensing steps substantially reduce the highest speed operation of an integrated circuit.
In order to improve the overall speed of the bit line sensing steps during memory operations, a bit line precharge circuit is conventionally used to maintain a constant voltage level on bit lines at least during a stand-by mode of operation.
An external supply voltage VCC or VCC-.alpha. (where .alpha. is an arbitrary constant) is generally selected as the given constant voltage level determined in accordance with a particular memory's design characteristics so as to maximize the speed of a read operation (where each bit line in an associated pair of bit lines is complementarily biased in active read mode).
A bit line precharge circuit serves to precharge a bit line pair to the given constant voltage level. Such precharge voltage signals however adversely contribute in the creation of parasitic capacitances along the bit line circuit paths due to the general complexity thereof.
Researchers continue to seek ways to improve the current driving capacity of a bit line precharge circuit so as to provide more accurate memory cell readings by providing voltage levels along bit lines (i.e., supply voltage VCC or ground voltage VSS) which substantially correspond to bit line voltages after a write operation.
A conventional bit line precharge circuit 10 and interconnection thereof is illustrated in FIG. 1. A bit line precharge circuit is shown connected to one end of a bit line pair. The bit line precharge circuit 10 includes a first bit line set of precharge transistors P1 and P2 normally turned on and a second set of bit line precharge transistors P3 and P4 controlled by bit line precharge signal .PHI.PRE. This signal is generally derived from a word line enable buffer. Alternatively, bit line precharge signal .PHI.PRE may also be derived from a combination of an output of a word line enable buffer with the output from an address transition detector, the operation of which components is well understood in the art of semiconductor memory devices.
Signals of bit lines BL1 and BL1 are transferred through transfer transistors N1, P5, N2 and P6 to data lines DL1 and DL1 by column decoding signals Y1 and Y1 when memory cells M1, . . . , M1 are selected.
Supply voltage VCC is continuously provided to bit lines BL1 and BL1 regardless of the mode of operation as the first set of bit line precharge transistors P1 and P2 are normally turned on. This is necessary as it improves the switch to a memory cell read operation immediately after a write operation.
The second set of bit line precharge transistors P3 and P4 are enabled (turned on) in read mode to prevent overdriving already active precharge transistors P1 and P2. As a result, the speed of a read operation can be significantly improved as bit lines BL1 and BL1 can be precharged much faster up to supply voltage level Vcc following a write operation.
Conversely, precharge transistors P3 and P4 can be disabled (turned off) during a write mode/operation as sufficiently less current drive is necessary and adequately provided by active precharge transistors P1 and P2.
Bit line precharge circuit 10 is shown arranged at one end of the present chip configuration for a more convenient chip layout.
FIG. 2 shows a memory cell array layout of a chip including the precharge circuit interconnection in FIG. 1. As illustrated therein, first and second bit line precharge circuits 110 and 120 are arranged on the same side of a memory cell array 100.
Each of the second set of bit line precharge transistors P3 and P4 in the conventional bit line precharge circuit 10 of FIG. 1 is increased in size to enhance current driving capacity. In so doing, however, the load on line 11 which transmits bit line precharge signal .PHI.PRE is necessarily increased. As a result, read mode is delayed for a sufficient time until all the second set of bit line precharge transistors P3 and P4 are enabled immediately following a write operation.
This bit line precharge delay which results from the switch from an appropriate bit line voltage (i.e., supply voltage level Vcc or ground voltage level Vss) during a write operation to a constant voltage precharge level in preparation for a read operation, sufficiently degrades a memory device's maximum speed of operation.
In order to overcome the load problem discussed above, precharge circuit configurations have been proposed in which the size of a first set of bit line precharge transistors P1 and P2 is increased while the size of a second set of bit line precharge transistors P3 and P4 is decreased.
However, when such a configuration is implemented in a memory array layout as in FIG. 2, a bit line precharge time delay difference .tau. (where .tau.=R.multidot.C, and R and C denote bit line parasitic resistance and bit line parasitic capacitance, respectively) occurs during a read operation--immediately following a write operation--between memory cells M1 and Mi respectively arranged nearest to and farthest from bit line precharge circuit 10.
Furthermore, when all first and second bit line precharge transistors P1, P2, P3 and P4 are enabled for a read operation, a bit line current difference per unit time is present between memory cells M1 and Mi which serves to degrade a memory cell current sensing operation.